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Extracting Components & Pins from ODB++

One major advantage that using ODB++ has (over Gerber/Drill) is that there is generally component information embedded in the ODB++ database that is needed by the EM simulator program.

The ASCII Description of Components

The component is described in the ASCII output of NETEX-O. The component section is "flat" i.e. we don't describe each component as a symbol and then place it. Here is the information that should be supplied:

begin_component
reference_designator,component_name
Xins,YIns, rotation
outline x1,y1,x2,y2,x3,y3 ...
height z
value xxxx
pin_label,x_coord, ycoord, padstack, net_index
pin_label,x_coord, ycoord, padstack, net_index 
pin_label,x_coord, ycoord, padstack, net_index 
pin_label,x_coord, ycoord, padstack, net_index 
pin_label,x_coord, ycoord, padstack, net_index
.
.
.
end_component

Note that since this description is flat, the pin coordinates and component outline coordinates are not in any way affected by the component insertion coordinate or rotation unless one needed to compute backwards to a symbol definition.

The reference designator should be unique in a given file/circuit. [required]

The component name need not be unique. For example if a 0204 capacitor is used 10 times, each placement must have a unique reference dsignator (i.e. C1, C2, C3 ...) but the name might always be C0204.

the component outline is used to render the body. It is generally a square but could be a polygon.

the component height if it is known could be used to render the component body in 3D. [optional]

The pin label is generally a numeral such as 1,2,3 but could also be a alphanumeric such as A5. In PCB databases the combination of the reference designator and the pin label are generally concatenated with a period i.e. pin 1 of C1 is referred to as C1.1 [rquired]

pin xcoord and ycoord are generally agreed to be located in the center of the pin's padstack. [required]

padstack - this points to name of a pad stack that is enumerated in detail somewhere else in the ASCII file. The padstack generally has a 2D geometry associated with it such as a circle, donut, square, rectangle or oblong. The pad stack generally also has a single layer associated with it - either the top or bottom metal layer for most PCBs. [required]

net_index - each pin is associated with a net - normally the index into the net table. [required]

One item that needs examination is whether we need to support padstack rotation for the pins. We should look at the input data in ODB++ to make this determination.

By itself this component section in the ASCII file is of little use. However it acts as the "source" for component sections in various target outputs for NETEX-O. Two such targets are shown below:




Ansoft Neutral File Components

Artwork has been producing Ansoft's neutral file (ANF) for quite some time. However until now, we have never produced component information which means that except in cases where the simulation was for conductors only, the user must manually enter component pin and node information. With ODB++ we now have the ability to extract component info.

The Ansoft component file is used along with the Ansoft Neutral Format (ANF) version 2 to define the location and electrical properties of components in a printed circuit board. References to net number, layer number, padstack number, and geometrical coordinates must be consistent with information defined in the ANF file. The format for the *.cmp file is shown below.

"X" lines specify pin parameters. The line below is not broken in normal use:


X <net #> <start layer #> <end layer #> 
    <padstack #> <x> <y> <angle in degrees> 
        <part number> <reference designator> <pin number>


The net #, layer #s and padstack # correspond to values defined for nets, layers and padstacks in the ANF V2.

Example 1

B_RES "R28" "CC0603"
X 1 2 2 48 -3382.000000 -1650.000000 0.000000 CC0603 R28 2
X 438 2 2 48 -3318.000000 -1650.000000 0.000000 CC0603 R28 1
"???" "???" "???" "???"
E_RES

The four "???" strings at the end of each record in the CMP file are placeholders for the nominal element value, the parasitic capacitance, the parasitic inductance and parasitic resistance, respectively. Set to "???" if these values are unknown.



Example 2

B_CAP C54 CC0603
X 2 2 2 48 2257.000000 -900.000000 180.000000 CC0603 C54 2
X 266 2 2 48 2193.000000 -900.000000 180.000000 CC0603 C54 1
10n 0 1n 0.2
E_CAP
The record above defines a capacitor with a nominal value of 10nF, a parasitic inductance of 1nH and a parasitic resistance of 0.2ohms.


3DI Components

Artwork recently developed an interface to Allegro that uses the 3DI format as a "neutral" file to AWR's Microwave Office. The MWOffice program needed some component information that was not part of the standard 3DI contents so we added a component section to 3DI just for MW Office.

3DI Component Syntax

The component section begins with the keyword COMPONENT. Each component begins with the keyword COMP.

COMPONENTS                         begin component section
COMP                               begin component
REFDES <ref_designator>            reference designator
CLASS <class i.e. IC,DIE,PASSIVE>  properties (if known)
NAME <name>
DEVICE <device_name>
VALUE <value>
PART_NAME <part_name>
PINS <number of pins>              enumeration of pins
PIN <pin_num> <x> <y> <net (index to NET TABLE)>
PIN 10 108.81 93.65 231
PIN 9 108.81 91.11 321

REFDES - each time a component is placed it is assigned a unique reference designator. This is because a component symbol (such as a chip resistor) might be used 10-100 times in the same circuit. While the basic component does not change, the placement coordinates will be different and the value of the component may be different.

Note that in 3DI all components are "flat" i.e. one does not define them first as a symbol and then place the symbol with an insertion point and rotation.

CLASS - this is just an attribute taken from Allegro/APD. Allegro divides components into certain classes such as IC (for a die chip), IO (for a connector or BGA substrate with pins, PASSIVE for a chip resistor, capacitor or inductor. Note: Class names are not always correctly applied within Allegro. We have seen passive components defined as IC or IO.

NAME - a name assigned to this component by Allegro.

DEVICE - a device name assigned to this component [optional]

VALUE - a value for this component. It might be empty or it might be appropriate for a capacitor or resistor. [optional]

PART_NAME - yet another name; we don't know how this differs from NAME or DEVICE. [optional]

PINS - the number of pins for this component

PIN - a specific pin followed by its label, its x,y position and an index to its net.

The asc23di.exe program will be updated to read the component section and to pass that information into 3Di. It will also read the component outline and height and render a 3D box for the component body.





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