Differences between Cadence Allegro Native STEP output and Artwork's STEP Output
In Allegro v16.6 Cadence added the ability to export a STEP 3D model for the etch classes. While this seemed a very good option for FEA simulation engineers, Allegro board designers have reported that the resulting output is not really useful for FEA purposes.
Let's run through a small example - we'll output STEP directly from Allegro and import it into SolidWorks; We will then output Artwork's 3Di from the same .brd file and convert it into STEP using Artwork 3Di2STEP (optimized for FEA.)
Exporting STEP Natively from Allegro
We'll start with a multi-layer PCB layout (we've removed a lot of the geometries to keep things from getting too big)
We'll then use the File | Export | Step menu pick to open the Step Export dialog:
We are interested in getting out the conductor layers (etch/pin/via) and the vias connecting each layer.
Clicking on Export produces a STEP file very quickly.
Exporting 3Di to Get to STEP
In order to export 3Di we have installed Artwork's AWROut plug-in. We start the program and see the dialog.
The main dialog needs no user input. We'll go to the Settings dialog and adjust our parameters.
Next, we'll use 3DVu to open the 3Di file and export STEP.
Start by opening the file and selecting File | Export | STEP for FEA
File Size Differences?
When we look into our directory we see that the two STEP files produced vary greatly in size! The Artwork file is more than 100X larger than the STEP file produced by Allegro.
Can this be correct? Let's open both files in SolidWorks and find out.
Importing the Allegro Native STEP Output into SolidWorks
We'll start by importing the Allegro STEP into SolidWorks. It imports very quickly and this is what we see initially:
Looks good. But upon closer examination, not so much.
First, the board is one solid body (there are "holes" drilled into it where the vias pass through.) However there's no internal spaces to allow for the conductors. For FEA you can't have conductor and dielectric occupying the same physical space.
Let's hide the board and check out the conductors.
Holy Cow! What happened to our internal layers? They're gone!
And our vias. Where are the vias? Gone.
Let's have a closer look at the top and bottom conductor layers and see what's there:
Our conductors have no thickness. Zero. They are not really solid bodies. Just surfaces. This won't do. You can't do a 3D simulation with zero thickness! Well at least we have nice contours. We can just extrude everything ourselves.
Well, apparently not. SolidWorks won't let you extrude two surfaces that touch or interfere. And it appears that our traces interfere with our pads and our pads interfere with our shapes.
Well, the STEP from Allegro imported but we'll not be able to do any 3D FEA simulations unless we spend quite a few hours redrawing and cleaning things up. Not what we hoped for.
Importing the STEP from Artwork
OK, now let's do the same with the STEP file from Artwork. I think I'm beginning to understand why it is 100X bigger than the Allegro STEP file.
After waiting quite a while for SolidWorks to digest this large STEP file we see:
Looks pretty similar to what we initially saw with the Allegro STEP. So let's dig in a little deeper by turning off all the dielectric geometries and just examine the conductors.
This is quite different than what we saw coming in from Allegro. We have all the inner layers and we have all the vias as solid bodies. Now it makes sense why the STEP file was so much larger.
Let's get a better look at the via geometries. I've turned off all the conductor layers except bottom and all the vias except those that run from bottom to top.
Notice that the vias are a single long cylinder with six sides. Also notice that where a via passes through a conductor layer there is a corresponding hole to remove any interference that would trip up the mesher.
I've turned on the top layer and one of the inner layers just to give another look.
If I turn off the via geometries you can see the holes in the conductor geometries where the vias pass through more clearly.
In order to eliminate air gaps internal to the PCB stackup, we build the dielectric geometries from two separate sources. The board between conductors is pretty straightfoward. However on each conductor layer we have to generate the "fill in" dielectric by performing a Boolean operation between the conductor geometries for each layer and the board outline.
If your intent is to do some sort of 3D FEA simulation or analysis on your PCB then the direct STEP output from Cadence Allegro is not usable - you are better off using Artwork's 3Di extractor and converting to STEP to get a model that has been optimized for FEA simulators.