Automated SRAM Identification

Steve DiBartolomeo, Applications Manager
last revised: November 15, 2010

Large ASICs can have thousands of SRAM blocks scattered across the layout. These SRAM regions are inspected using a different algorithm than the logic regions and require that we extract and separate the "care areas." Generating such regions manually is extremely time consuming. We describe a software routine that automates the process and can handle large ASICs in an hour.

Objectives

Extract all SRAM unit cells and convert them to care areas.

Do not require the user to know anything about the cell names or file hierarchy

Process large GDSII/OASIS files in 60 minutes or less including load/identify/merge.

The user will load the layout file, specify the POLY and SRAM support layers.

Program Flow

The SRAM ID program flow is shown below. You can "click" on functional boxes to get details and notes.

Scaling Issues

The biggest hurdle with the SRAM ID is the sheer size and complexity of today's ASIC layouts - GDSII files of 30-50GB with 500,000 cell definitions and which can contain anywhere from 50-5000 SRAM blocks of varying size scattered throughout the layout.

This approach divides the heavy pattern recognition computations into chunks defined by each SRAM block. Once the SRAM support layer has been processed and the windows of interest are known, the work of examining each SRAM block and extracting the care areas is highly parallelized.

This page discusses how to profile a large layout file prior to running the SRAM_ID and how to track down potential problems ...GO