Advanced Digital Lithography (DLT) is emerging as a critical manufacturing technology for next-generation semiconductor packaging, heterogeneous integration, and advanced substrate fabrication. Unlike conventional mask-based lithography approaches, DLT enables direct imaging workflows capable of supporting extremely fine geometries, rapid design iteration, and large-format substrates such as advanced organic materials and glass panels used in AI-era chiplet architectures.
As semiconductor devices continue scaling beyond traditional monolithic designs, manufacturers are increasingly adopting 2.5D and 3D heterogeneous integration technologies that combine multiple chiplets into a single high-bandwidth package. These advanced packaging flows require highly accurate data preparation and imaging pipelines capable of preserving geometric integrity throughout the conversion and manufacturing process.

One of the major challenges in these workflows is the reliable conversion of manufacturing databases such as ODB++ into downstream lithography formats including GDSII. During this process, geometric operations, scaling, rasterization, trapezoidal conversion, and image preparation must be performed without introducing unintended modifications or data corruption. Even small discrepancies can become significant when processing sub-micron features across very large substrates.
To address this requirement, Artwork Conversion Software developed an automated ODB++ verification workflow designed specifically for advanced digital lithography environments. The solution validates the integrity of generated GDSII data against the original ODB++ source database through automated raster-based comparison and visual verification technologies.
The workflow combines four integrated software modules operating within a unified scripting and automation environment.
At the center of the workflow is SFGEN, Artwork’s high-performance data preparation engine for advanced lithography applications. SFGEN performs the conversion of ODB++ manufacturing data into GDSII while supporting a wide range of geometric and image-processing operations required in modern packaging flows.
These operations include mirroring, scaling, offset and sizing functions, annotations, image corrections, and conversion into trapezoidal data structures optimized for downstream rasterization and writer processing. The software is designed to efficiently process extremely large datasets associated with advanced packaging substrates and panel-level manufacturing.
QisMRip rasterizes the processed GDSII output generated by SFGEN into high-resolution TIFF image data suitable for verification and comparison analysis.
The module is optimized for handling large-format datasets while maintaining the precision required for sub-micron lithography applications. By converting the final GDSII data into a rasterized representation, QisMRip enables direct visual and raster comparison against the original source database.

ODBRIP performs rasterization of the original ODB++ source database using matching resolution and imaging parameters.
This creates a normalized bitmap representation of the original manufacturing data, allowing direct one-to-one comparison with the rasterized GDSII output generated downstream in the process. Maintaining identical rasterization conditions between both datasets helps ensure accurate verification results and minimizes interpretation ambiguity.
RasterCompare performs automated pixel-level analysis between the rasterized ODB++ source image and the rasterized GDSII output image.
The software generates a detailed difference report identifying any detected geometric discrepancies between the two datasets. To eliminate insignificant rasterization artifacts and avoid false positives, RasterCompare includes a user-defined pixel tolerance threshold that automatically filters out small one- or two-pixel variations commonly introduced during rasterization processes.
This allows engineering teams to focus attention on meaningful differences that may impact downstream lithography or manufacturing accuracy.
As advanced digital lithography workflows move toward sub-micron geometries on Gen 8.5-class glass panels (approximately 2.2 × 2.5 meters), rasterized image datasets can become extremely large, particularly at resolutions approaching 1/8 micron (203,200 DPI).
At these resolutions, full-panel raster files may exceed the practical memory limits of conventional image comparison approaches.
To address this challenge, RasterCompare automatically partitions the full raster extents into smaller tiled processing windows and compares corresponding regions from the ODB++ and GDSII TIFF datasets independently.
The dynamic tiling strategy is based on image dimensions, the resolution, and available memory, allowing very large panel datasets to be processed efficiently without exceeding system memory.

RasterCompare, ODBRIP, and QisMRip are fully multithreaded, enabling parallel processing of tiled raster regions across multiple CPU cores. This architecture typically allows full-panel verification at 1/8 micron resolution to complete in less than 20 minutes while maintaining pixel-level comparison accuracy across very large substrates.
For example, a 500 × 500 mm design rasterized at 1/8 micron pixel resolution can generate approximately 2 TB of raster data. By processing the design in tiled regions rather than as a single image, the workflow can efficiently perform verification on standard engineering workstations with as little as 128 GB of RAM.
RasterCompare can generate either GDSII output highlighting detected differences in their original layout locations, or TIFF/BMP image output for visual inspection and analysis.
VLBV provides an integrated bitmap viewing and visual comparison environment for engineering review and analysis.
Engineers can visually inspect rasterized datasets, review highlighted differences, zoom into specific regions, and analyze detected discrepancies within a unified graphical environment. The software helps simplify the review process while providing an additional layer of confidence before data enters downstream imaging and writer stages.
The increasing complexity of semiconductor packaging is driving demand for highly reliable data preparation and verification workflows. As digital lithography technologies continue evolving toward larger substrates, finer geometries, and higher-density interconnects, automated verification is becoming an important part of maintaining manufacturing accuracy and process confidence.
Artwork’s automated verification workflow was developed to support emerging digital lithography technologies associated with next-generation packaging initiatives, including large-format substrates, glass panel processing, and sub-2-micron interconnect structures.
By combining automated verification, raster comparison, and visual analysis into a unified workflow, the solution helps semiconductor manufacturers improve confidence in critical ODB++ to GDSII conversion processes while reducing risk in increasingly complex manufacturing environments.
