Netex-G is first and foremost a geometry engine. It builds "nets" from conductor and via information by unionizing all the conductors on each layer of a PCB. Think of each resulting geometry as a "net" on that particular layer.
The program then looks at the via layers above and below each conductor layer to see where the vias intersect conductors. It is able then to follow the connection from one layer to the next using this via/conductor intersection.
The end result is a list of conductors and vias that are electrically connected. By default NETEX-G assigns net names starting at Net1, Net2, Net3 .... until all groups have been accounted for.
Adding Net Name and Pin Information
Without any additional information we are not yet able to provide a conventional net list. However there are a couple of ways to add labels for both nets and pins (aka nodes).
Import an IPC-D-356 file along with the Gerber/Drill files which does include pin labels on top/bottom with the pin coordinates and also associates net names with those pins.
Import an AIF file (typically output by IC package design tools)
Import an ODB++ file which has a component and netlist section.
Netex-G dumps a number of files into the "working" directory (user defines this directory in the settings) and the one that contains the desired net/pin information is always named: *_rewrite_mrg_neall_ascexfilt.txt.
Note: Files in the working directory are erased when Netex-G is closed unless the user has set a preference to retain them.
The ASCII file is broken into many sections and it evolved over the years as sections were added. Hence, you will find net and pin information scattered in multiple locations.
The Net Table
There is a section starting with B_NET_TABLE and terminated by E_NET_TABLE that contains indices for the net names. This allows other sections to reference the index number instead of spelling out what might be a long net name. This section looks like the sample below:
B_NET_TABLE 1 Net1 2 Net2 3 Net3 4 Net4 5 Net5 6 +5V 7 24MHZ 8 CLKIN 9 Net9 10 GND . . . 95 Net151 96 $$$3116 97 Net153 E_NET_TABLE
The COMP Section
The COMP section lists each component that is placed (this information usually is derived from ODB++ input to Netex-G). This section begins with B_COMP and is terminated by E_COMP.
Each component that is placed starts with B_COMP_REF and is terminated by E_COMP_REF
[B_COMP_ATTR - E_COMP_ATTR][B_COMP_PIN - E_COMP_PIN]The Pin List
Within each component placement section, there is a list of pins that begins withB_COMP_PIN and is terminated by E_COMP_PIN.
Each line in this section defines a pin and its attributes. These include (from left to right)
A sample of a placed component is shown below:
B_COMP_REF R1 52070.000000 13970.000000 1 PACKAGE_NAME pcbdata_PKG7 COMP_NAME R1_8W_1206 COMP_EXTENT 4953.000000 1524.000000 52070.000000 13970.000000 0.000000 M0 PART_NAME R1_8W B_COMP_ATTR E_COMP_ATTR B_COMP_PIN 1 50355.500000 13970.000000 1 3 0.000 M0 80 2 53784.500000 13970.000000 1 3 0.000 M0 6 E_COMP_PIN E_COMP_REF
One can see that pin 1 is located at 50.3555,13.97 mm on stackup 1 (the top of the PCB) using the padstack found at index 3. Rotation = 0.00, no mirroring and it is attached to the net with index 80.
One could write a simple program that would iterate through all the component placements, extract the reference designator, extract the pin labels and the net index and build a conventional netlist from this information. It would not include any "nets" of conductors extracted by NETEX-G that were electrically isolated from the component pins, however.
This section (which can be identified by searching for the string LIBRARY starting in column 1) lists all of the conductor and via geometries sorted by net.
The first line of each group of conductors/vias (i.e. a NET) start with the keyword NET.
Following that keyword is the net's name.
Following the net name are pins or nodes.
Each node entry has 4 fields:
A sample is shown below:
LIBRARY PCBDATA_REWRITE_MRG_NEALL.GDSSCL unit:UM grid:1000 NET 24MHZ R5.1 8445500 43180000 1 Y1.3 11404600 39141400 1 U7.1 10795000 15494000 1 VIA 1 7 635000 13 7874000 13589000 ENDEL VIA 1 7 635000 13 10795000 13716000 ENDEL BOUNDARY 1 0 7852850 13145000 7895150 13145000 7937260 13149020 7978790 13157030 8019380 13168950 8058650 13184670 . . . ENSTR
Collecting all the netlist information from the NET lines should result in the same netlist as generated by iterating through the component pins with the exception that this approach will include any conductor/via nets that are electrically isolated from the pins.