This page summarizes the changes and fixes to each version of the ACAD2APD.
New versions of ACSLIB and Wirebond with support for AutoCAD 2017 and AutoCAD2018.
These versions make use of 32/64 bit registry hives and break out HKLM from HKCU for install settings/user settings.
New versions of ACSLIB and LayoutGen with support for AutoCAD 2017.
New Installer for ACSLIB and LayoutGen.
This version identifies whether a symbol definition is on the TOP or BOTTOM and gives it the correct outline layers on the appropriate subclass.
Added the ability to create a via layer (circles or polygons) and the ability to specify which layers this via layer interconnects. Currently there must be a shape above and below a via to make the interconnection but we soon intend to upgrade this to support pins either above and below the via.
Updated the importer to handle the new vias.
added a new model for the gull wing lead. This one represents more accurately the lead that leaves the package body horizontally, drops down and then move horizontally again to the output pin on the PCB.
The wing via was not getting the correct net assigned to it. Earlier revision to the net tracing module designed to handle stacked die broke the wing via net connection. This has been fixed.
adds a filter to prevent the user from marking entities such as lines and arcs as shapes.
adds a filter to clean up net names that don't meet the Cadence rules - i.e. lower case and net names with spaces or special characters.
The line linker was having problems with extremely short lines segments. They are now filtered out.sybmol builder
The symbol builder did not retain the IC vs IO setting and would reset to IC. This has been fixed.
This is the first beta release for the LayoutGen program.
This is acslib containing the required library support for LayoutGen 0.92
This is the first beta release for the import module running inside of APD 16.2.