Qckvu includes an interface to Mentor Graphics Calibre RVE program. RVE is used to nagivate through the error files produced by design rule checks (DRC). RVE supports error files generated by Mentor's Calibre, Synopsis' (Avanti) Hercules, Cadence's Assura and other tools used by chip engineers to verify that there are no violations in the design rules of the chip layout.

The verification program reads the final GDSII layout and compares each geometry against a complex set of design rules. If a rule violation is detected, the type of violation and its location is written to an ASCII file (known as the "error" file.) For large dense chips, many such violations can turn up and a design engineer needs to review each error. Some errors will need to be corrected but other errors can be safely ignored and some errors may be generated incorrectly due to the way the rule set is defined.

The RVE program can read such an error file, organize the errors by type, cell or location and present this large amount of data to a designer. If a designer wishes to actually "see" the error he needs to open the GDSII file and zoom in to the specified cell and coordinate. This can be done automatically; clicking on an error in RVE sends a message to Qckvu telling it which cell to open and where to look. RVE can also send Qckvu highlighting polygon in order to isolate the error on the display screen.