Introduction

Artwork has developed a number of software tools to automate the layout of wafer level masks. These are most commonly used for fan-in and fan-out redistribution while building packages directly onto a wafer. These tools greatly reduce the time required to lay out the wafer mask and reduce errors generated by a more manual approach.

GDS-SR is a very powerful tool for stepping out one or more die across a wafer. In includes support for knocking out or substituting individual devices, producing SINF output and handing input of individual die or reticles.

Hextract is a Boolean that clips the die devices along the edge of the wafer to a perfectly round boundary. It can be directed to keep or delete the small polygons that cross the boundary depending on what each layer's process requirements demand.

WLayGen reads a number of different wafer map formats and produces a layout in GDSII format which is viewed in Qckvu3. It can also read reticle shot map parameters provided by a foundry and produce a layout from that data. By overlaying the shot map and wafer map data, the user can determine the exact placement of each die on the wafer and use this as a template for the redistribution mask.

GDSFILT is a power GDSII utility that can merge multiple GDSII files, substitute one cell for another and extract individual layers from a GDSII layout. It is used to drop in special features into a wafer mask or to separate a design into individual layers.

If the RDL circuit is designed by the customer (COTS), then the packaging mask designer often needs to verify that all line widths, gaps and enclosures meet the design rules. The lightweight DRC does this quickly and easily and costs 20X less than a full DRC used for integrated circuits.

Smart Die scans a chip and extracts the coordinates and sizes of the pad openings. This is often the very first step in designing the RDL unit cell in tools such as Cadence APD/SIP.

These AutoCAD based plug-ins help speed up the documentation of the wafer masks and of the unit cell design.

Glossary and Reference

Below we document various parameters, geometries and formats used in the generation of wafer masks.

Wafer Diameter/Margin/Notch

Step & Repeat Parameters

Dealing with Reticle Data

Knock Out Die to Reveal Underlying Features

Drop in Alignment and Test Die

Leaving Sacrificial Die for Clipping

Creating a SINF output File

Clip Array to a Round Circle

Removing Slivers during Clip

Merging Data from External Files

Final Mask Set Output

Viewing and Checking Results

Auto Documentation of Unit Cell

Auto Documentation of Wafer Layout

wafer map files - formats and conversion